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Virtex-6 FPGA Data Sheet: DC and Switching Characteristics
Table 73: Sample Window
Symbol
Description
Device
-3
Speed Grade
-2 -1
-1L
Units
T SAMP
Sampling Error at Receiver Pins (1)
All
510
560
610
670
ps
T SAMP_BUFIO
Sampling Error at Receiver Pins using
BUFIO (2)
All
300
350
400
440
ps
Notes:
1.
2.
This parameter indicates the total sampling error of Virtex-6 FPGA DDR input registers, measured across voltage, temperature, and
process. The characterization methodology uses the MMCM to capture the DDR input registers’ edges of operation. These measurements
include:
- CLK0 MMCM jitter
- MMCM accuracy (phase offset)
- MMCM phase shift resolution
These measurements do not include package or clock tree skew.
This parameter indicates the total sampling error of Virtex-6 FPGA DDR input registers, measured across voltage, temperature, and
process. The characterization methodology uses the BUFIO clock network and IODELAY to capture the DDR input registers’ edges of
operation. These measurements do not include package or clock tree skew.
Table 74: Pin-to-Pin Setup/Hold and Clock-to-Out
Symbol
Description
-3
Speed Grade
-2 -1
-1L
Units
Data Input Setup and Hold Times Relative to a Forwarded Clock Input Pin Using BUFIO
T PSCS /T PHCS
Setup/Hold of I/O clock
–0.28/1.09 –0.28/1.16 –0.28/1.33 –0.18/1.79
ns
Pin-to-Pin Clock-to-Out Using BUFIO
T ICKOFCS
Clock-to-Out of I/O clock
4.22
4.59
5.22
5.63
ns
Revision History
The following table shows the revision history for this document:
Date
06/24/2009
07/16/2009
08/19/2009
09/16/2009
Version
1.0
1.1
1.2
2.0
Description of Revisions
Initial Xilinx release.
Revised the maximum V CCAUX and V IN numbers in Table 2, page 2 . Removed empty column from
Table 3, page 3 . Revised specifications on Table 20, page 13 . Updated Table 38, page 22 and added
notes 1 and 2. Revised T DLYCCO_RDY , T IDELAYCTRL_RPW , and T IDELAYPAT_JIT in Table 53, page 41 .
Updated Table 58, page 46 to more closely match the DSP48E1 speed specifications. Updated
T TAPTCK /T TCKTAP in Table 59, page 49 . Updated XC6VLX130T parameters in Table 68 through
Table 70, page 59 .
Added values for -1L voltages and speed grade in all pertinent tables. Added V FS and notes to Table 1
and Table 2 . Removed DV PPIN from the example in Figure 2 . Added networking applications to
Table 41, page 25 . Changed and added to the block RAM F MAX section in Table 57, page 44 including
removing Note 12. Changed F PFDMAX values and corrected units for T STATPHAOFFSET and T OUTDUTY
in Table 64, page 52 . Updated Table 71, page 60 .
Added Virtex-6 HXT devices to entire document including GTH Transceiver Specifications . Updated
speed specifications as described in Switching Characteristics , includes changes in Table 51 ,
Table 57 , Table 58 , and Table 66 through Table 70 . Comprehensive changes to Table 14 , Table 15 , and
Table 16 . Added conditions to D VPPOUT and revised description of T OSKEW in Table 17 . Removed V ISE
specification and note from Table 18 . Added note 3 to Table 23 . Updated note 3 in Table 24 . Updated
LVCMOS25 delays in Table 44 . Updated specification for T IOTPHZ in Table 46 . Removed T BUFHSKEW
from Table 71, page 60 and added values for T BUFIOSKEW . Added values in Table 74 .
DS152 (v3.6) March 18, 2014
Product Specification
www.xilinx.com
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